• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:

    公开号:SE1150867A1
    申请号:SE1150867
    申请日:2011-09-23
    公开日:2012-03-31
    发明作者:Rajesh Kumar Malhan
    申请人:Denso Corp；
    IPC主号:
    专利说明:

    Connected to a rear surface of the nI-type SiC base portion J1, so that a current flows between a drain and a source when the channel region is formed in the channel layer J8.
    According to the configuration described above, however, an electrical connection between the embedded gate layer J10 and the gate wire J12 is made via the ditch J13, which penetrates the source layer J5 of the nite type and the buffer layer J4 and extends into the SiC layer J3 of p * type. In this type of structure, the width of the ditch J13 becomes large, because the interlayer insulating film J11 and the gate wire J12 are arranged in the ditch 13, and thus sufficient scaling can not be achieved. For this reason, it is desirable to provide a structure that can scale down a contact structure between the embedded gate layer J10 and the gate wire J12. Although the above description refers to a semiconductor device that uses SiC as a semiconductor material, it is also applicable to a semiconductor that uses other semiconductor materials.
    In view of the foregoing, it is an object of the present invention to provide a semiconductor device having a JF ET which can scale down a contact structure between an embedded gate layer and a gate wire.
    According to a first aspect, the present invention comprises a semiconductor device with a JFET (junction field-effect transistor). The JFET unit includes a base member, an operating layer, a semiconductor layer, a source layer, a first trench, a channel layer, an upper gate layer, a first gate wire, a second gate wire, and a drain electrode. . The base part has a main surface made of a semiconductor material, and has a first conductivity type. The drift layer is arranged above the base part, is configured as an epitaxial layer, and has the first type of conductivity. The semiconductor layer is arranged above the operating layer and has a second type of conductivity. The source layer is arranged above the semiconductor layer, which has the first type of conductivity, and has an impurity concentration greater than the operating layer. The first trench penetrates the source layer and the semiconductor layer and extends into the operating layer.
    The duct layer is arranged in the first ditch, and has the first type of conductivity. The upper gate layer is arranged on a surface of the channel layer in the first ditch, and has the second type of impurity. The first gate wire is electrically connected to the upper gate layer.
    The second gate wire is electrically connected to an embedded gate layer, which is the part of the semiconductor layer adjacent to the channel layer. The source electrode is electrically connected to the source layer. The drain electrode is electrically connected to a rear surface of the substrate. The semiconductor device further comprises a second trench and a contact-embedded layer. The second trench penetrates the source layer and extends into the embedded gate layer. The contact-embedded layer completely fills the second ditch, and has the second type of conductivity. The second gate wire is connected to the contact-embedded layer, so that the second gate wire is connected to the embedded gate layer via the contact-embedded layer.
    According to the above aspect semiconductor device, an electrical connection is made between the embedded gate layer and the second gate wire with the contact embedded layer arranged in the second trench. Thereby, the width of the second trench, in which only the contact-embedded layer is arranged, can be reduced, compared with the width of a trench of a traditional semiconductor device where an intermediate layer insulating film and a gate wire, etc., are arranged in the trench. Therefore, a semiconductor device with the JFET unit can scale down the contact structure between the embedded gate layer and the second gate wire.
    According to a second aspect, the present invention comprises a manufacturing method of a semiconductor device with a JFET comprising preparing a semiconductor substrate.
    The semiconductor substrate comprises: a base member having a major surface, made of semiconductor material, and having a first conductivity type; an operating layer formed above the base portion by epitaxial growth, and having the first type of conductivity; a semiconductor layer formed above the operating layer and having a second conductivity type; and a source layer formed above the semiconductor layer, has an impurity concentration greater than the operating layer, and has the first type of conductivity. The manufacturing method further comprises: forming a first trench which penetrates the source layer and the semiconductor layer and extends into the operating layer; forming a channel layer having the first conductivity type on a surface of the semiconductor substrate comprising an inside of the first trench; forming a second trench separate from the first trench so that the second trench penetrates the channel layer and the source layer and extends into the semiconductor layer; forming a layer of a second conductivity type in the first trench and in the second trench, so that the layer with the second conductivity type is formed on a surface of the channel layer in the first trench; and removing the layer with the second conductivity type and the channel layer above the source layer by planarizing a surface of the semiconductor substrate after forming the layer with the second conductivity type, so that an upper gate layer is formed in the first trench and a contact embedded layer is formed in the second ditch. In the above, the upper gate layer is formed from the channel layer and the layer with the second conductivity type in the first trench, and the contact-embedded layer is formed by the layer of the second conductivity type in the second trench. The manufacturing method further comprises: forming an interlayer insulating film on a surface of the semiconductor substrate and forming contact holes for exposing the source layer, the upper gate layer and the contact embedded layer, respectively, in the interlayer insulating film; forming a source electrode electrically connected to the source layer through a first of the contact holes, a first gate wire electrically connected to the upper gate layer through a second of the contact holes, and a second gate wire electrically connected to the contact-embedded layer through a third of the contact holes; and forming a drain electrode electrically coupled to the base portion of a rear surface of the semiconductor substrate.
    According to the manufacturing method described above, it is possible to manufacture a semiconductor device with a JFET which can scale down a contact structure between an embedded gate layer and a gate wire.
    According to the above and other objects, features and advantages of the present invention will become more apparent from the following detailed description taken in conjunction with the accompanying drawings. In the drawings: Fig. 1 is a cross-sectional view showing a SiC semiconductor device with a JFET of a first embodiment; Fig. 2 is a cross-sectional view showing a manufacturing process of a SiC semiconductor device shown in Fig. 1; Fig. 3 is a cross-sectional view showing a manufacturing process of the SiC semiconductor device following Fig. 2; Fig. 4 is a cross-sectional view showing a manufacturing process of the SiC semiconductor device following Fig. 3; Fig. 5 is a cross-sectional view showing a manufacturing process of the SiC semiconductor device following Fig. 4; Fig. 6 is a cross-sectional view showing a manufacturing process of the SiC semiconductor device following Fig. 5; Fig. 7 is a cross-sectional view showing a manufacturing process of the SiC semiconductor device following Fig. 6; Fig. 8 is a cross-sectional view showing a manufacturing process of the SiC semiconductor device following Fig. 7; Fig. 9 is a cross-sectional view showing a manufacturing process of the SiC semiconductor device following Fig. 8; Fig. 10 is a cross-sectional view showing a manufacturing process of the SiC semiconductor device following Fig. 9; Fig. 11 is a cross-sectional view showing a manufacturing process of the SiC semiconductor device following Fig. 10; Fig. 12 is a cross-sectional view showing a manufacturing process of the SiC semiconductor device following Fig. 11; Fig. 13 is a cross-sectional view showing a manufacturing process of the SiC semiconductor device following Fig. 12; Fig. 14 is a cross-sectional view showing a manufacturing process of the SiC semiconductor device following Fig. 13; Fig. 15 is a cross-sectional view showing a manufacturing process of the SiC semiconductor device following Fig. 14; Fig. 16 is a cross-sectional view showing a manufacturing process of the SiC semiconductor device following Fig. 15; Fig. 17 is a cross-sectional view showing a manufacturing process of the SiC semiconductor device following Fig. 16; Fig. 18 is a cross-sectional view showing a manufacturing process of the SiC semiconductor device following Fig. 17; Fig. 19 is a cross-sectional view showing a manufacturing process of the SiC semiconductor device following Fig. 18; Fig. 20 is a cross-sectional view showing a manufacturing process of the SiC semiconductor device following Fig. 19; Fig. 21 is a cross-sectional view showing a manufacturing process of the SiC semiconductor device following Fig. 20; Fig. 22 is a cross-sectional view showing a manufacturing process of the SiC semiconductor device following Fig. 21; Fig. 23A is a cross-sectional view showing a p-type region of a protective ring structure in an outer resistant portion of the first embodiment; and Fig. 23B is a cross-sectional view showing a protective ring structure in which a p-type region is configured only by a pi-type SiC layer; Fig. 24 is a cross-sectional view showing a SiC semiconductor device with a JFET according to a second embodiment; Fig. 25 is a cross-sectional view showing a manufacturing process of a SiC semiconductor device shown in Fig. 24; Fig. 26 is a cross-sectional view showing a SiC semiconductor device with a JFET according to a third embodiment; and Fig. 27 is a figure showing a JFET of a prior art SiC semiconductor device.
    Embodiments are described based on the accompanying drawings. The same references are used throughout to refer to equal or corresponding parts.
    (First Embodiment) A first embodiment will be described. Fig. 1 is a cross-sectional view of a SiC semiconductor device with a JFET according to the present embodiment. In the following with reference to this drawing, a structure of SiC semiconductor device with JFET is described.
    The SiC semiconductor device shown in Fig. 1 is formed by an n * type SiC base part 1, which uses a (0001) Si surface as its main surface. For example, the n1-type SiC base member 1 used in the present embodiment has a specific electrical resistance of from mo> o-cm tm 1x1o2 ° Q-cm, and a thickness of from 250 μm to 400 μm (e.g. 350 μm). um). An operating layer 2 of n 'type is formed as a film on the main surface of the SiC base part 1 of n1 type. This n 'type operating layer 2 has, for example, an n-type impurity concentration of from 1x1015 cm -1 to 1x101 ° cm * (for example 5.0x1015 cm -1), and a thickness of from 5.0 μm to 15.0 μm (for example 13.0 μm).
    A p1 type SiC layer 3, an n 'type or p' type SiC buffer layer 4, and an n 'type source layer 5 are formed in order on a surface of the operating layer 2 of n'-typ. The p1-type SiC layer 3 has, for example, a p-type impurity concentration of from 1x101 ° cm -1 to 1x102 ° cm -1 (for example 5.0x1018 cm -1), and a thickness of from 1.0 μm to 2 , 0 um (for example 1.4 um). The buffer layer 4 has, for example, an n-type or p-type impurity concentration of from 1x1014 cm -1 to 1x1016 cm -1 (eg 1x1015 cm -1), and a thickness of from 0.1 μm to 0.5 μm (t). ex. 0.3 μm). The n * type source layer 5 has a greater impurity concentration than the n 'type operating layer 2. For example, the n-type source layer 5 has an impurity concentration of from 5x1018 cm -1 to 1x102 cm -1 (for example 2.0x1019 cm -1), and a thickness of from 0.5 μm to 1. 5 um (e.g. 1.0 um). As can be seen from the above description, the SiC semiconductor device according to the present embodiment is formed by using a semiconductor substrate 6, on which the layers 2 to 5 are formed in order on the SiC base part 1 of n * type.
    Specifically, the SiC semiconductor device according to the present embodiment comprises a JFET formation part (cell part) R1, an outer peripheral breakdown proof portion R2 and a JFET separating part. (element separation portion) R3. In the JFET formation part R1, JFETs are formed by a plurality of cells. The outer resistive portion R2 is shaped so as to enclose an outer periphery of the JFET formation portion R1. The JFET separating portion R3 is arranged at a boundary area between the JFET formation portion R1 and the outer resistive portion R2.
    The JFET formation part R1 is configured as follows. A trench 7 is formed in the JFET formation portion R1 of the semiconductor substrate 6. A channel layer 8 made of n 'type SiC and an upper gate layer 9 made of pI type SiC are embedded in the trench 7. The trench 7 has one such depth so that the ditch 7 penetrates the SiC layer 3 of the pipe type, the buffer layer 4 and the source layer 5 of the nite type and extends into the operating layer 2. The ditch 7 is shaped to have its longitudinal direction, for example the direction perpendicular to the surface of the drawing . The channel layer 8 has, for example, an n-type impurity concentration with a concentration of from 1x10 16 cm -1 to 5x10 "cm -1 (for example 1.0x10" cm -1), and a thickness of from 0.1 μm to 1.0 pm (for example 0.3 pm). The upper gate layer 9 has, for example, a p-type impurity concentration of from 1x10 8 cm 3 to 1x10 2 cm 3 (for example 1.0x10 19 cm 3), and a thickness of from 2.0 μm to 5.0 μm (e.g. 3.0 μm). Surfaces of the channel layers 8, the upper gate layer 9 and the source layer 5 of the nite type are in the same plane.
    Due to the configuration described above, a part of the SiC layer adjacent to the channel layer 8 is used as an embedded gate layer 10. An increased amount of depletion layer extending into the channel layer 8 is interlaced between the upper gate layer 9 and the embedding gate layer 10, can be controlled by applying voltage to the upper gate layer 9 and the embedded gate layer 10.
    An intermediate insulating film 11, which may comprise an LTO film, etc., is formed on the surfaces of the channel layer 8, the upper gate layer 9 and the source layer 5 of the n-type. The gate wire 12 is electrically connected to the upper gate layer 9 via a contact hole 11a formed in the intermediate insulating film 11. This structure enables control of voltage application to the upper gate layer via the gate wire 12.
    A ditch 13 is formed in the semiconductor substrate 6. A contact-embedded layer 14 is formed so as to completely fill the ditch 13. The ditch 13 penetrates the n-type source layer 5 and the buffer layer 4 and extends into the embedded layer 10. The pi-type layer 14 in the ditch 13 is in contact with the embedded gate layer 10. The pi-type contact-embedded layer 14 has, for example, an impurity concentration of p-type 10 with a concentration of 1x10 "cm -1 to 1x10 ° om ”(e.g. 1.0x1 01 9 cm'3), and a thickness of 1.0 μm to 3.0 μm (e.g. 1.5 μm). The gate wire 12 is electrically connected to the contact-embedded layer 14 via a contact hole 11b formed in the intermediate insulating film 11. This structure enables control of voltage application to the embedded gate layer 10, which is connected to the contact-embedded layer 14. of p * type via gate wire 12.
    When a bottom surface of the ditch 13 is a Si side and a side surface of the ditch 13 is an a-side, it is possible to provide the contact type embedded layer 14 with such an impurity concentration that: a portion of the contact type embedded layer 14 is formed on the bottom surface of the ditch 13 has a higher impurity concentration than other part of the contact-embedded layer 14 of pïtype formed on the side surface of the ditch 13. This is due to a plane direction dependence of concentration of mature crystals, and the concentration of mature crystals on The si-side is larger than on the a-side. In order to achieve the above-mentioned concentration ratio, a planar direction for the main surface of the n-type SiC base part 1 can be set to, for example, (0001) Si side.
    According to the above-described configuration, a PN junction of a contact portion between the contact type embedded layer 14 and the nite type source layer 5 may have a high breakdown voltage (breakdown resistance). Furthermore, it is possible to reduce the disk resistance at the contact portion between the p-type contact-embedded layer 14 and the embedded gate layer 10 based on the fact that the impurity concentration of the p * -type embedded layer 14 can be kept high at the contact portion between the p-type contact-embedded layer 14. and the embedded gate layer 10.
    The impurity concentration can be the same over an entire growth direction (thickness direction) of a contact-embedded layer 14 of pi-type. Alternatively, to improve the degradation voltage at the contact portion of the p * type contact embedded layer 14 and the nite type source layer 5, the pite type contact embedded layer 14 may have such a concentration that the impurity concentration gradually increases with increasing distance from the contact portion between the contact-embedded layer 14 of the pi-type and the source layer 5 of the n * -type. In this case, it is possible to provide a high breakdown voltage (breakdown resistance) to a PN junction through the contact portion between the contact portion of the contact type embedded layer 14 and the nite type source layer 5. Formation of the above-mentioned structure can be difficult if the contact-embedded layer 14 of the type is formed by ion implantation, due to the fact that a conductivity type of the source layer 5 n n-type needs to be inverted. the structure described above is easily performed if the contact type embedded layer 14 is formed by epitaxial growth.
    Furthermore, the disk resistance can be increased at an interface between the contact type embedded layer 14 and the embedded gate layer 10, by a decrease in the impurity concentration of the contact type embedded layer 14, according to the configuration described above. For this reason, it may be better to set the impurity concentration of the contact type embedded layer 14 with respect to both improving the degradation voltage and increasing the disk resistance at the PN junction. For example, about 10 "cm'3 may be desirable.
    A silicide layer 12a is provided as a portion of the gate wire 12 contacting the upper gate layer 9 or the embedded gate layer 10. The silicide layer 12a is formed by a metal reaction of at least a portion of the gate wire 12 with Si. in the upper gate layer 9 or the embedded gate layer 10. This silicide layer 12a reduces the contact resistance.
    Through the contact hole 11c formed in the intermediate insulating film 11, a source electrode 15 contacts the source layer 5 of the nite type. A silicide layer 15a is provided as part of the source electrode 15 contacting the nitype source layer 5. The silicide layer 15a is formed by reacting metal of at least a portion of the source electrode 15 with Si in the n-type source layer 5. This silicide layer 15a reduces the contact resistance. The intermediate insulating film 16 is shaped to cover the source electrode 15 and the gate wire 12. A source wire 17 is formed above the intermediate insulating film 16. A contact hole 16a is formed in the intermediate insulating film 16. The source wire 17 is electrically connected to the source electrode 15 through this contact hole 16a.
    A drain electrode 18 connects the rear surface of the n-type SiC base member 1 to form the JFET unit. The drain electrode 18 comprises a Ti film, a Ni film and an Au film, which in turn are laminated. A silicide layer 18a is provided as part of the drain electrode 18 in contact with the nI-type SiC base member 1. The silicide layer 18a is formed by reaction of metal of at least a part of the drain electrode 18 with Si in the SiC base part 1 of n * type. This silicide layer 18a reduces the contact resistance. To protect the JFET unit configured above, a surface of the formation part R1 of the JFET unit is covered with a protective film 19.
    The outer resistant part R2 is configured as follows. In the outer resistant part R2, the source layer 5 is of the n-type and the buffer layer 4 is removing 10 from the semiconductor substrate 6. A layer 20 of the p * type is formed on a surface of the SiC layer 3 of the p * type from which the layers 4, 5 are removed. This pi-type layer has, for example, a p-type impurity concentration having a concentration of from 1x1018 cm -1 * to 1x102 ° cm -1 (for example 1.0x1019 cm -1), and a thickness of from 2.0 μm to 5 cm 3. 0 pm (for example 3.0 pm).
    Several frame-shaped ditches 21 are formed at regular intervals, which penetrate the layer 20 of the pipe type and the SiC layer 3 of the pipe type and extend into the operating layer 2 of the n-type and surround the JFET formation part R1. The widths d1 to dn of the ditches 21 (where n is the number of ditches 21) gradually increase with increasing distance from the JFET formation part R1.
    Each ditch 21 is filled with the intermediate insulating film 11 or the intermediate insulating film 16. In this way, a protective ring structure is formed by dividing a p-type region into a plurality of regions of the ditches 21 and the insulating films 11, 16 in the ditches 21. A recess 22 is located outside the protective ring structure. The recess 22 is formed on the semiconductor substrate 6 by removing the n-type source layer 5 and the buffer layer 4, so that the recess 22 surrounds the protective ring structure. A wire portion 23 is arranged in this recess through the intermediate insulating film 11, 16. In this way, an EQR (Equi-Potential Ring) structure is formed. A surface of the above-configured outer resistant part R2 is covered with the protective film 19.
    The JFET separation portion R3 is configured to transmit a breakthrough current into the source wire 17 when a breakthrough occurs at the outer resistive portion R2 in reverse bias events; thereby, the JFET separating portion R3 prevents breakthrough current from flowing through the JFET formation portion R1.
    Specifically, the JFET separating part R3 is configured as follows. In the JFET separating part R3, the source layer 5 is also of the nite type and the buffer layer 4 is removed from the semiconductor substrate 6. A layer 20 of the pite type is formed on a surface of the SiC layer 3 of the pite type from which the above layers 4, 5 are removed. Furthermore, a plurality of frame-shaped ditches 31 penetrate the p * -type layer and the pi -type SiC layer 3 and extend into the n '-type operating layer 2 and surround the JFET formation part R1 at regular intervals. Each ditch 31 is filled with the intermediate insulating film 11 or the intermediate insulating film 16. Furthermore, an extraction electrode 32 is electrically coupled to the layer 20 of the type formed at an area outside the ditch 31. This extraction electrode 32 is arranged above the intermediate insulating film 11, so that the extraction electrode 32 which is electrically connected to the pi-type layer 20 through a contact hole 11d formed by the intermediate insulating film 11. Further, this extraction electrode 32 is electrically connected to the source wire 17 through a contact hole 16b formed in the intermediate the insulation film 16. This configuration allows, when a breakthrough occurs at the outer resistive part R2 at times of reverse bias, that it is possible to transmit the breakthrough current into the source wire 17 via the extraction electrode 32.
    A silicide layer 32a is provided as part of the extraction electrode 32 contacting the type 20 layer.
    The silicide layer 32a is formed by reacting metal of at least a portion of the extraction electrode 32 with Si in the layer 20 of the type. The silicide layer 32a provides reduced contact resistance.
    The semiconductor device with the JFET unit is configured to have the structure described above.
    In the above-configured SiC semiconductor device with the JFET unit, the channel layer 8 is clamped by an depletion layer extending from the upper gate layer 9 and the embedded gate layer 10 to the channel layer 8, when a gate voltage is not applied to the upper gate layer 9 and the embedded gate layer 10 via the gate wire 12. From this position, the depletion area extending from the upper gate layer 9 and the embedded gate layer 10 is reduced, when the gate the voltage is applied to the upper gate layer 9 and the embedded gate layer 10 via the gate wire 12. Consequently, a channel region is formed in the channel layer 8, and a current flows between the source electrode 15 and the drain electrode 18 through the channel region. In this way, the JFET unit according to the present embodiment can function as a normally-off element. In the above-configured SiC semiconductor device, an electrical connection is achieved between the embedded gate layer 10 and the gate wire 12 of the contact type embedded layer 14. Accordingly, the width of the ditch 13 can be reduced, in which only the contact-embedded layer 14 of the pipe type is arranged, as compared with the ditch J13 in the traditional SiC semiconductor device as shown in Fig. 27, where the intermediate insulating film J11 and the gate wire J12 are arranged in diket J13.
    In the following, a manufacturing method for the above-described configuration of semiconductor device with JFET of the present embodiment is described. Figs. 2 to 22 are cross-sectional views showing manufacturing processes of the SiC semiconductor device with JFET according to the present embodiment. In Figs. 2 to 22, each of the JFET formation part R1, the outer resilient part R2 and the JFET separation part R3 is shown during the manufacturing process, and further, an adjustment key part R4 is shown pre-adjustment in trench forming or muster. The ditch shaping, patterning or the like is performed with reference to a recess shaped adjustment key portion R4 even though a specific description of the adjustment key portion R4 is not given in the following description.
    Fig. 2 first shows preparation of the semiconductor substrate 6 in which the n 'type operating layer 2, the p "type SiC layer 3, the buffer layer 4, and the nite type source layer 5 are formed, which in turn are formed on the nI-type SiC base part 1. Here, the n '-type operating layer 2 has an n-type impurity concentration of 50x10 "cm'3, and the thickness is 13.0 μm. The p * -type SiC layer 3 has a p-type impurity concentration of 5x1018 cm -1 and a thickness of 1.4 μm. The buffer layer 4 has an n-type or p-type impurity concentration of 1.0x1015 cm -1, and a thickness of 0.3 μm. The n * type source layer 5 has an n-type impurity concentration of 20x10 "cm -1, and a thickness of 1.4 .mu.m. The thickness of the n 'type operating layer 2, the SiC layer 3 of the pipe type and the buffer layer the fourth layer 4 is the same as at the completion of the semiconductor device shown in Fig. 1, however, the source layer 5 of the n * type is thicker than at the completion of the SiC semiconductor device shown in Fig. 1.
    As shown in Fig. 3, a masking film 40 having a thickness of, for example, 2 μm is then formed on a surface of the semiconductor substrate 6, i.e. on a surface of the source layer 5 of n * type. The masking film may be, for example, a TEOS film. Then, the masking film 40 is patterned by a photoprocessing process, and apertures are formed at an area where the trench 7 is to be formed in the semiconductor substrate 6, and at an area where the adjustment key portion R4 is formed.
    As shown in Fig. 4, dry etching is then performed by means of the masking film 40 as a mask, so that the ditch 7 and the adjusting key 41 are formed to such a depth that they penetrate the SiC layer 3 of type, the buffer layer 4 and the source layer 5 of n ' type and extends into the operating layer 2 of n 'type. Then the masking film 40 is removed.
    Furthermore, as shown in Fig. 5, an n 'type layer 42 is formed to form the channel layer 8 by epitaxial growth. In this epitaxial growth, the n 'type layer 42 is formed with, for example, the n-type impurity concentration of 1x10 16 cm -1 to 5x10 "cm'3 (for example 1.0x10" cm'3), and a thickness of 0.1 μm. to 1.0 μm (e.g. 0.3 μm) on a complete surface of the semiconductor substrate 6 including an inside of the ditch 7 and an inside of the alignment key 41. Further shown in Fig. 6 after a masking film 43 as a TEOS film or the like has been formed on a surface of the n 42 type layer 42, the masking film 43 is patterned so that openings are formed at an area where the outer resistant part R2 is to be formed and at an area where the JFET separating part R3 is to be formed. formed, in addition to an area where the ditch 13 is to be formed.
    Then, as shown in Fig. 7, the ditch 13 penetrating the n 'type layer 42, the nite type source layer 5 and the buffer layer 4 is formed and extends into the pite type SiC layer 3, by using the masking film 43 in dry etching as a masking, and the SiC layer 3 is exposed by removing the source layer 5 of the pipe type and the buffer layer 4 in the outer resistant part R2 and the JFET separating part R3. To expose the pi-type SiC layer 3 above, the dry etching thickness in the above is set greater than the thickness of the pi-type source layer 5 and that of the buffer layer 4. Then the masking film 43 is removed.
    Then, as shown in Fig. 8, the p * -type layer 44 grows epitaxially with, for example, a p-type impurity concentration of from 1x10 -8 cm "to 1x110 ° cm" (for example, 1.0x1019 cm from 2.0 μm to 5.0 μm (for example 3.0 μm) on a complete surface of the semiconductor substrate 6 including a surface of the layer 42 of the n 'type, and an inside of the ditch 13, the outer resistant part R2 and the JFET separating part R3. Accordingly, the pi-type layer 44 is also formed on the surface of the n 'type layer 42 in the ditch 7, and the ditch 7 is filled with the n' type layer 42 and the pi-type layer 44. The surface of the layer 44 of the pipe type is arranged in addition above the surface of the buffer layer 4.
    Then, as shown in Fig. 9, the pi-type layer 44, the n '-type layer 42 and the pi-type source layer 5 are planarized by mechanical polishing for planing. If the surface of the semiconductor substrate 6 in the JFET formation part R1, as previously described, is planarized to the depth of the surface of the p "type layer 44 in the outer resistant part R2 and the JFET separating part R3, it is possible to prevent the pi-type layer 44 and the n '-type layer 42 from remaining on the surface of the pi-type source layer 5 while it is possible to allow the pi-type source layer 5 to remain.Then a required thickness of a surface part through RIE (Reactive lon Etching), and the removal thickness is adjusted by surface planing, then surface polishing is performed by CMP (Chemical Mechanical Polishing), in this way the channel layer 8, the upper gate layer 9 and the contact-embedded layer are formed. 14 of the pipe type from the layer 44 of the p * type and the layer 42 of the n 'type remain in the ditches 7 and 13.
    As shown in Fig. 10, a masking film 45, for example a TEOS film, is then formed to have a thickness of, for example, 2 μm on a surface of the semiconductor substrate 6. Then, the masking film 45 is patterned by a photoprocessing process, so that the openings are formed above the upper gate layer 9, the contact-embedded layer 14 of the pipe type, and a surface of the layer 20 of the pipe type in the JFET separating part R3. Then, the impurity concentrations in the upper gate layer 9, the p-type contact-embedded layer 14, and a surface of the p * -type layer 20 in the JFET separating portion R3 are increased by ion implanted by Al ions. As described above, an ion-implemented region has, for example, a p-type impurity concentration of from 1x102 ° om * to 5x102 ° om ”(e.g. 4.0x1019 cm -1), and a thickness of from 0.1 μm to 0.5 μm (e.g. 0 , 3 pm). Then, the masking film 45 is removed, and another masking film 46, for example a TEOS film, is formed to have, for example, a thickness of 2 μm on a surface of the semiconductor substrate 6, according to Fig. 11. Then the masking film 46 is patterned by a photoprocessing process, so that openings are formed at areas where the ditch 21 and the depression 22 in the outer resistant part R2 are to be formed and at an area where the ditch 31 in the JFET-separating part R3 is to be formed. As shown in Fig. 12, dry etching is then performed by the masking film 46 to form the ditch 21, the depression 22 and the ditch 31, which penetrate the pi-type layer 20 and the pi-type SiC layer 3 and extend into the operating layer 2 of n ' type. Then the masking film 46 is removed.
    As shown in Fig. 13, the intermediate insulating film 11 comprising an LTO film is then formed, and then the semiconductor substrate 6 is ground on a back side, i.e., a surface of the nI-type SiC base portion 1 opposite to a surface to which the operating layer 2 of n'-typ formas sli- pas. Then, the intermediate insulating film 11 is patterned by a mask (not shown) and the contact holes 11a to 11d are formed according to Fig. 14. Further, according to Fig. 15, a metal film 47 made of metallic material is formed which causes a silicide reaction, such as Ni and the like. they, on a surface of the intermediate insulating film 11 comprising insides of the contact holes 11a to 11d. Then, the metal film 47 is patterned so that the metal film 47 remains on the insides of the contact holes 11a to 11d and their surroundings. Further according to Fig. 16, a metal film 48 made of metallic material which causes a silicide reaction such as Ni and the like is formed on the back surface of the semiconductor substrate 6. By a silicidation process by heat treatment, the metallic materials in the metal film 47 and the metal film 48 are formed. react with Si in SiC by silicidation. For example, heat treatment is performed at 1000 degrees C for 10 minutes. Thereby, according to Fig. 17, the slicidal layers 12a, 15a, 32a are formed on a front side of the semiconductor substrate 6 and the silicide layer 18a is formed on the back side of the semiconductor substrate 6. Then unreacted parts of the metal films 47, 48 are removed.
    As shown in Fig. 18, a metal film made of metallic material such as Ti and the like is formed on a surface of the intermediate insulating film 11 comprising insides of the contact holes 11a to 11d. Then, this metal film is patterned so that the gate wire 12, the source electrode 15 and the extraction electrode 32 are formed. Then, according to Fig. 19, the intermediate insulating film 16 comprising, for example, an LTO film is formed and patterned so that a contact hole 16a is formed to expose the extraction electrode 32.
    Furthermore, according to Fig. 20, a film for wire material is formed and patterned, for example, of Al, so that the source wire 17 and the wire part 23 are formed. Then, according to Fig. 21, the protective film 19 comprising, for example, a polyimide resin film (PIQ film) is formed so that the protective film 19 covers the source wire 17 and the wire portion 23. Then, according to Fig. 22, The drain electrode, in turn, comprises a Ti film, a Ni film and an Au film stacked on the rear surface of the semiconductor substrate 6. Dicing is performed in parts of chip.
    Accordingly, the SiC semiconductor device with JFET shown in Fig. 1 is complete.
    In the above-described SiC semiconductor device with the JFET unit according to the present embodiment, the electrical connection between the embedded gate layer 10 and the gate wire 12 of the contact-embedded layer 14 is formed. This allows the width of the ditch 13, in which only the contact type embedded layer 14 is arranged, to be reduced, compared with the width of the ditch J13 in the prior art SiC semiconductor device of Fig. 27 in which the intermediate insulating film J11 and the gate the wire J12, etc are arranged in the ditch J13. Therefore, the SiC semiconductor device with JFET can reduce the contact structure between the embedded gate layer 10 and the gate wire 12. In connection with the outer resistant part R2, an additional advantage can be achieved. This will be described with reference to Fig. 23.
    Fig. 23A is a cross-sectional view of the outer resilient portion R2 in which the p-type region of the protective ring structure is formed by the p * type SiC layer 3 and the pi type layer 20. Fig. 23B is a cross-sectional view of the outer resistant part R2 in which the p-type region of the protective ring structure is formed only by the p * type SiC layer 3. As shown in Figs. 23A and 23B, the p-type region of the protective ring structure can be formed by using the pi-type SiC layer 3 and the pf-type layer 20 or only by the pi-type SiC layer 3. However, as shown in Fig. 23B, when the p-type region is formed only by the p-type SiC layer 3, it is conceivable that the p-type SiC layer 3 is made too thin in the process shown in Fig. 7. In contrast, when not only the pi-type SiC layer 3 but also the p * -type layer 20 are arranged as the p-type region, it is possible to ensure sufficient thickness of the p-type region to constitute the protective ring structure. In addition, the p-type region constituting the protective ring structure formed only by the pi-type SiC layer 3, the height of the position of the surface of the JFET formation part R1 at the semiconductor substrate 6 can not coincide with the position of the surface of the protective ring of the outer resistant de If the p-type region as opposed to the protective ring structure is formed by using the pi-type SiC layer 3 and the p * -type layer 20, the height of the surface of the JFET formation part R1 at the semiconductor substrate 6 may coincide with the surface of the protective ring 6. position of the external resistance give part R2. This makes it possible to promote flattening of the surface of the semiconductor substrate 6.
    (Second Embodiment) A second embodiment will be described. The present embodiment may be a modification of the first embodiment in the configuration of the JFET separation part R3.
    For other points, the present embodiment may be the same as for the first embodiment, and thus only parts which are separate from the first embodiment may be described.
    Fig. 24 is a cross-sectional view of a SiC semiconductor device with a JFET according to the present embodiment. As shown in Fig. 24, the source layer 5 remains of the nite type and the buffer layer 4 in the JFET separation part R3. A trench 50 is formed at a portion of the semiconductor substrate 6 connecting the extraction electrode 32. A p * type contact layer 51 is formed in the trench 50. The ptype contact layer 51 formed in the trench 50 is located deeper than the nite type source layer 5 and the buffer layer 4. The pi-type contact layer 51 has such a depth that the p "-type contact layer 51 contacts the pi-type SiC layer 3. This structure means that in the event of a breakthrough, a breakthrough current can be transmitted from the pi-type SiC layer 3. and the contact type 51 layer 51 to the source wire 17 via the extraction electrode 32.
    In this way, the JFET separation part R3 is also configured so that the nitype source layer 5 and the buffer layer 4 remain the JFET separation part R3. A path for transmitting the breakthrough current can be formed by the pi-type contact layer 51.
    A manufacturing method for a SiC semiconductor device with JFET designed as above may be substantially the same as that in the first embodiment. In particular, it may be sufficient to replace the process of Fig. 6 in the first embodiment with a process as described in Fig. 25. In particular, as shown in Fig. 25, when the masking film 43 is patterned, openings are formed at an area of the outer resistive member. R2 of the semiconductor substrate 6, an area where the trench 13 is to be formed and an area where the trench 50 is to be formed.
    Then, when the trench 13 and the outer resistive member are etched using this masking film 43, the trench 50 is formed. Then, the manufacturing process shown in drawings following Fig. 7 is performed. In this way, it is possible to manufacture a semiconductor device with JFET according to the present invention. embodiment.
    (Third Embodiment) A third embodiment will be described. A semiconductor device according to the present embodiment comprises a Schottky diode instead of the protective ring structure in the first embodiment in the outer resilient part R2. For other points, the present embodiment is essentially the same; consequently, only parts distinct from the first embodiment are described.
    Fig. 26 is a cross-sectional view of a SiC semiconductor device with a JFET according to the present embodiment. According to Fig. 26, a plurality of ditches 60 are formed at regular intervals in the outer resistant part R2. The ditches 60 penetrate the p * type SiC layer 3 and the pi type layer 20 and extend into the n 'type operating layer 2, and have a frame shape surrounding the JFET formation part R1. The depth of each trench 60 is less than the depth of the upper gate layer 9. A Schottky electrode 61 is arranged in the trench 60. The Schottky electrode 61 is made of a Schottky material such as Ti, and the Schottky electrode 61 as a contact takes the operating layer 2 of n 'type has a Schotty connector. As shown in the above description, the Schottky diode is constructed of the Schottky electrode 61, the operating layer 2 of the n 'type and the SiC base part 1 of the nite type.
    In this way, the SiC semiconductor device may include the Schottky diode. Manufacturing processes for the SiC semiconductor device according to the present embodiment may generally be the same as for the first embodiment. For example, before the process shown in Fig. 18, the intermediate insulating film 11 is patterned and the intermediate insulating film 11 in the outer resistant part R2 is removed. When forming the gate wire 12 and the extraction electrode 32 with, for example, Ti film, according to Fig. 18, the Schottky electrode 61 can also be formed.
    It should be noted that even if the Schottky diode is used in place of the protective ring structure according to the example described above, both the protective ring structure and the Schottky diode can be arranged together. In such a case, the guard ring structure can be arranged to encircle the Schottky diode. Although the majority of ditches 60 are arranged at regular intervals, in addition the majority of ditches 60 do not have to be arranged at regular intervals. Furthermore, a ditch 60 may be arranged instead of the plurality of ditches 60.
    (Other Embodiments) According to the embodiments described above, an n-channel type JFET is described by way of example. Nevertheless, the embodiments can be applied to a p-channel type JF ET, which can be obtained by reversing n-type and p-type in the embodiments described above.
    Furthermore, the upper gate layer 9 and the embedded gate layer 10 are connected to the same gate wire 12, according to embodiments described above. Alternatively, the upper gate layer 9 and the embedded gate layer 10 may be connected to different first and second gate wires, so that different electrical potentials are applicable to the upper gate layer 9 and the embedded gate layer 10, respectively.
    Further, the n * type source layer 5 is arranged above the pi-type SiC layer 3 through the buffer layer 4, in the embodiments described above. Since the buffer layer 4 can be arranged on a demand basis, alternatively the source layer 5 of nï type can be formed directly on the SiC layer 3 of pï type.
    Furthermore, in the embodiments described above, the SiC semiconductor is shown as an example of a semiconductor device. Alternatively, embodiments may be applied to a Si semiconductor device, and other wideband gap semiconductor devices. For example, the embodiments are applicable to a semiconductor device made of, for example, GaN, diamond, AIN.
    According to an example of embodiments, a semiconductor device with JFET can be configured as follows. The JFET unit comprises a base part (1), an operating layer (2), a semiconductor layer (3), a source layer (5), a first trench (7), a channel layer (8), an upper gate layer (9 ), a first gate wire (12), a second gate wire (12), and a drain electrode (18). The base part (1) has a main, surface is made of a semiconductor material, and has a first conductivity type. The drift layer (2) is arranged above the base part (1), configured as an epitaxial layer, and has the first type of conductivity. The semiconductor layer (3) is arranged above the operating layer (2) and has a second type of conductivity. The source layer (5) is arranged above the semiconductor layer (3), and has the first type of conductivity, and has an impurity concentration greater than the operating layer (2). The first trench (7) penetrates the source layer (5) and the semiconductor layer (3) and extends into the operating layer (2). The channel layer (8) is arranged in the first ditch (7), and has the first type of conductivity. The upper gate layer (9) is arranged on a surface of the channel layer (8) in the first trench (7), and has the second type of conductivity.
    The first gate wire (12) is electrically connected to the upper gate layer (9). The second gate wire (12) is electrically connected to an embedded gate layer (10), which is a part of the semiconductor layer (3) adjacent to the channel layer (8). The source electrode (15) is electrically connected to the source layer (5). The drain electrode (18) is electrically connected to a rear surface of the substrate (1). The semiconductor device further comprises a second trench (13) and a contact-embedded layer (14). The second trench (13) penetrates the source layer (14) into the embedded gate layer (10). The embedded gate layer (14) completely fills the second ditch, and has the second type of conductivity. The second gate wire (12) is connected to the contact-embedded layer (14), so that the second gate wire (12) is connected to the embedding gate layer (10) via the contact-embedded layer (14). .
    According to the semiconductor device above, an electrical connection is made between the embedded gate layer (10) and the second gate wire (12) of the contact embedded layer (14) arranged in the second trench (13). Thus, the width of the second ditch (13) can be reduced, because only the contact-embedded layer (14) is arranged there, compared to the width of a ditch of a traditional semiconductor device where an intermediate insulating film and a gate wire, etc. , are arranged in the ditch. Thus, the JFET semiconductor device can scale down a contact structure between the embedded gate layer (10) and the second gate wire (12).
    The semiconductor device as described above can be configured as follows. A bottom surface and a side surface of the handrail ditch (13) are Si-surface and a-surface, respectively. The impurity concentration of a part of the contact-embedded layer (14) arranged on the bottom surface of the second trench (13) is greater than it is on another part of the contact-embedded layer (14) arranged on the side surface of the second trench (13).
    In the above configuration, it is possible to reduce the disc resistance at a contact portion between the contact-embedded layer (14) and the embedded gate layer (10), while providing high breakthrough resistance by a PN junction between the contact-embedded layer ( 14) and the source layer (5). Alternatively, the contact embedded layer (14) may be configured to have a concentration distribution so that the impurity concentration increases with increasing distance from a contact portion with the source layer (5). In this configuration, it is also possible to provide a high breakthrough resistance at a PN junction between the contact-embedded layer (14) and the source layer (5). Formation of this structure can be difficult if the contact-embedded layer (14) is formed by ion implementation, because the conductivity type of the source layer (5) needs to be reversed; nevertheless, formation of this structure can be easily performed and the contact-embedded layer (14) is epitaxial growth.
    The semiconductor device above can be configured as follows. The semiconductor device with JFET further comprises: a cell part (R1) in which the JFET unit is formed; and an outer peripheral breakdown proof portion (R2) enclosing the cell portion (R1). In the outer resistant part R2, the source layer (5) is removed, and removal of the source layer (5) exposes a surface of the semiconductor layer (3), and a layer (20) of a second conductivity type is arranged on the exposed surface of the semiconductor layer (3). The outer resistant part R2 comprises a frame-shaped protective ring structure which surrounds the cell part (R1). The protective ring structure comprises: a plurality of third ditches (21) which penetrate the layer (20) of the second conductivity type and the semiconductor layer (3), and are arranged at regular intervals; and an insulating film (11, 16) arranged in the third trenches (21).
    As can be seen from the above description of the outer resistive part (R2), the layer (20) of the second conductivity type is arranged on the exposed surface of the semiconductor layer (3), after the source layer (5) has been removed. If the semiconductor layer (3), as above, becomes too thin upon removal of the source layer (5), the arrangement of the layer (20) of the second conductivity type can ensure sufficient thickness of a region of the second conductivity type to form the protective ring structure.
    The semiconductor device above can in this case be configured so that a surface of the layer (20) of the second conductivity type in the outer resistant part (R2), and respective surfaces of the source layer (5), the channel layer (8) and the upper gate layer (9) in the cell part (1) is on the same plane. In this configuration it is possible to easily perform planing of the surfaces of the source layer (5), the channel layer (8) and the upper gate layer (9) in the cell part (1). 10 15 20 25 30 35 21 The semiconductor device above can be configured as follows. The semiconductor device further comprises: a cell part (R1) in which a JFET is formed; an outer resilient member (R2) enclosing the base member (R1); and an element separating part (R3) arranged at a boundary position between the cell part (R1) and the outer resistant part (R2). In the outer resistive part (R2), the source layer (5) is removed, and removal of the source layer (5) exposes a surface of the semiconductor layer (3), and a layer (20) of a second conductivity type is arranged on the exposed surface of the semiconductor layer (3). In the element separating part (R3), an extraction electrode (32) is electrically connected to the semiconductor layer (3) via the layer (20) of the second conductivity type.
    In this way, the source layer (5) in the element separating part (R3) can be removed, and a path for transmitting a breakthrough current can be formed through the layer (20) of the second conductivity type.
    The semiconductor device above can be configured as follows. The semiconductor device further comprises: a cell part (R1) in which the JFET unit is formed; an outer resilient member (R2) enclosing the base member (R1); an element separating part (R3) arranged at a boundary position between the cell part (R1) and the outer resistive part (R2). The element separating part (R3) comprises: an extraction electrode (32) electrically connected to the semiconductor layer (3) located in the element separating part (R3); a fourth trench (50) penetrating the source layer (5) located in the element separating part (R3), and extending into the semiconductor layer (3) located in the element separating part (R3); and a contact layer (51) embedded in the fourth trench (50). The extraction electrode (32) is electrically connected to the semiconductor layer (3) via the contact layer (51).
    In this way, the source layer (5) can remain in the element separating part (R3), and a path for transmitting a breakthrough current can be formed by the contact layer (51).
    The semiconductor device above can be configured as follows. The semiconductor device further comprises: a cell part (R1) in which the JFET unit is formed; an outer resilient member (R2) enclosing the base member (R1); and Schottky diode. In the outer resistive part (R2), the source layer (5) is removed, and removal of the source layer (5) exposes a surface of the semiconductor layer (3), and a layer (20) of a second conductivity type is arranged on the exposed surface of the semiconductor layer (3). The Schottky diode comprises: a frame-shaped fifth trench (60) which encircles the cell part (R1), and penetrates the layer (20) of a second conductivity type and the semiconductor layer (3) and extends into the operating layer ( 2); and a Schottky electrode (61) arranged in the fifth trench (60) and electrically connected to the operating layer (2).
    According to a second example of embodiments, a manufacturing method can be provided. For example, the manufacturing method comprises preparing a semiconductor substrate (6).
    The semiconductor substrate (6) comprises: a base part (1) having a main surface, made of a semiconducting material, and having a first type of conductivity; an operating layer (2) formed above the base portion (1) by epitaxial growth, and having the first type of conductivity; a semiconductor layer (3) formed above the operating layer (2) and having a second conductivity type; and a source layer (5) formed above the semiconductor layer (3), which has an impurity concentration greater than the operating layer (2), and has the first type of conductivity.
    The manufacturing method further comprises: forming a first trench (7) which penetrates the source layer (5) and the semiconductor layer (3) and extends into the operating layer (2); forming a channel layer (8) having the first conductivity type on a surface of the semiconductor substrate (6) comprising an inside of the first trench (7); forming a second trench (13) separate from the first trench (7), so that the second trench (13) penetrates the channel layer (8) and the source layer (5) and extends into the semiconductor layer (3); forming a layer (44) of a second conductivity type in the first trench (7) and the second trench (13), so that the layer (44) of the second conductivity type is formed on a surface of the channel layer (8) in the first trench (7); and removing the layer (44) of the second conductivity type and the channel layer (8) above the source layer (5) by planarizing a surface of the semiconductor substrate (6) after forming the layer (44) of the second conductivity type, so that an upper gate layer 9 is formed in the first trench (7) and a contact-embedded layer (14) is formed in the second trench (13). In the above, the upper gate layer (9) is formed from the channel layer (8) and the layer (44) of the second conductivity type in the first trench (7), and the contact-embedded layer (14) is formed from the layer (44) of the second conductivity type in the second ditch (13). The manufacturing method further comprises: forming an intermediate insulating film (11) on a surface of the semiconductor substrate (6) and forming contact holes (11a to 11c) for exposing the source layer (5), the upper gate layer (9) and the contact embedded layer (14) in the intermediate insulating film (11), respectively; forming a source electrode (15) electrically connected to the source layer (5) by a first of the contact holes (11a to 11c), a first gate wire (12) electrically connected to the upper gate layer (9) by a second of the contact holes (11a to 11c), and a second gate wire (12) electrically connected to the contact-embedded layer (14) through a third of the contact holes (11a to 11c); and forming a drain electrode (18) electrically coupled to the base portion (1) on a rear surface of the semiconductor substrate (6). 10 15 20 25 30 35 23 According to the manufacturing method described above, it is possible to manufacture a semiconductor device with JFET which can scale down a contact structure between an embedded gate layer and a gate wire.
    In the above manufacturing method of the semiconductor device, an outer peripheral breakdown proof portion (R2) can be formed (R2) so that a cell portion (R1) is encircled in which the JFET unit is to be formed. In the formation of the second trench (13), the source layer (5) in the outer resistive part (R2) can be removed to expose a surface of the semiconductor layer (3). In the formation of the layer (44) of the second conductivity type, the layer (44) of the second conductivity type can be further formed on the exposed surface by removing the source layer (5), of the semiconductor layer (3). When flattening the surface of the semiconductor substrate (6), the flattening can be performed against a surface of the layer (44) of the second conductivity type formed in the outer resistant part (R2).
    As described above, when flattening the surface of the semiconductor substrate (6) is performed on the surface of the layer (44) of the second conductivity type formed in the outer resistant part (R2), it becomes possible to easily flatten the surface of the semiconductor substrate (6). In the manufacturing method of the semiconductor device, an element separating part (R3) can be formed at a boundary position between the cell part (R1) and the outer resistive part (R2). When forming the second trench (13), the source layer (5) in the element separating part (R3) can be removed to expose a surface of the semiconductor layer (3). When forming the layer (44) of the second conductivity type, the layer (44) of the second conductivity type can be further formed on the exposed surface, which is exposed by removing the source layer (5), of the semiconductor layer (3). When forming the intermediate insulating film (11) and forming the contact holes (11a to 11c), an additional contact hole (11d) can be formed in the intermediate insulating film (11), to expose the layer (44) of the second conductivity type in the element separating part (R3). When forming the source electrode (15) and the second gate wire (12), an extraction electrode (32) can be formed. The extraction electrode (32) is electrically connected to the layer (44) of the second conductivity type through the further contact hole (11d) formed in the intermediate insulating film (11) in the element separating part (R3). By using this manufacturing method, it is possible to manufacture the semiconductor device in which the source layer (5), in the element separating part (R3), can be removed and a path for transmitting breakthrough current can be formed. of the extraction electrode (32). In the manufacturing method of the semiconductor device, an element separating part (R3) can be formed at a boundary position between the cell part (R1) and the outer resistant part (R2). In forming the second trench (13), a third trench (50) may be formed which penetrates the source layer (5) and extends into the semiconductor layer (3), the third trench (50) may be formed in the element separating part (R3). When forming the layer (44) of the second conductivity type, the layer (44) of the second conductivity type can be further formed in the third trench (50) in the element separating part (R3). When flattening the surface of the semiconductor substrate (6), the flattening can be performed so that the layer (44) of the second conductivity type remains only in the third trench (50) thereby forming a contact layer (51). When forming the intermediate insulating film (11) and forming the contact holes (11a to 11c), an additional contact hole (11d) can be formed in the intermediate insulating film (11) for exposing the contact layer (51) in the element separating part (R3). When forming the source electrode (15) and the second gate wire (12), an extraction electrode (32) can be further formed. The extraction electrode (32) is electrically connected to the contact layer (51) through the further contact hole (11d) formed in the intermediate insulating film (11) in the element separating part (R3). By using this manufacturing method, it is possible to manufacture the semiconductor device in which the source layer (5) can remain in the element separating part (R3), and a path for transmitting a breakthrough current can be formed by the contact layer (51).
    Although the invention as described above has been described with reference to various embodiments thereof, it is to be understood that the invention is not limited to the embodiments and constructions described above. The invention is intended to cover various modifications and equivalent arrangements.
    权利要求:
    Claims (11)
    [1]
    A semiconductor device having a junction field-effect transistor (JFET), comprising: a JFET comprising: a base member (1) having a major surface, made of a semiconductor material, and having a first conductivity type; an operating layer (2) arranged above the base (1), is configured as an epitaxial layer, and has the first type of conductivity; a semiconductor layer (3) arranged above the operating layer (2) and having a second conductivity type; a source layer (5) arranged above the semiconductor layer (3), which has the first type of conductivity, and has a greater impurity concentration than the operating layer (2); a first trench (7) which penetrates the source layer (5) and the semiconductor layer (3) and extends into the operating layer (2); a channel layer (8) arranged in the first trench (7) and having the first conductivity type; an upper gate layer (9) arranged on a surface of the channel layer (8) in the first trench (7), and having the second conductivity type; a first gate wire (12) electrically connected to the upper gate layer (9): a second gate wire (12) electrically connected to an embedded gate layer (10), the embedded gate layer (10) is a part of the semiconductor layer (3) adjacent to the channel layer (8); a source electrode (15) electrically connected to the source layer (5); and a drain electrode (18) electrically connected to a rear surface of the substrate (1), a second trench (13) penetrating the source layer (5) and extending into the embedded gate layer (10). ); and a contact-embedded layer (14) which completely fills the second trench (13), and has the second type of conductivity, the second gate wire (12) being connected to the contact-embedded layer (14), so that the second gate wire ( 12) is connected to the embedded gate layer (10) via the contact embedded layer (14). 10 15 20 25 30 35 26
    [2]
    The semiconductor device with the JFET unit according to claim 1, wherein: a bottom surface and a side surface of the second trench (13) are Si-side and a-side, respectively; and the impurity concentration of a part of the contact-embedded layer (14) arranged on the bottom surface of the second trench (13) is greater than that at another part of the contact-embedded layer (14) arranged on the side surface of the second trench (13) ).
    [3]
    The semiconductor device with the JFET unit according to claim 1 or 2, comprising: a cell part (R1) in which the JFET unit is formed an outer peripheral breakdown proof portion (R2) as encloses the cell part (R1), wherein in the outer resistant part (R2), the source layer (5) is removed, and removal of the source layer (5) exposes a surface of the semiconductor layer (3), and a layer (20). ) of a second conductivity type is arranged on the exposed surface of the semiconductor layer (3); and the outer resistant part (R2) comprises a protective ring structure having a frame shape surrounding the cell part (R1), the protective ring structure comprising: a plurality of third trenches (21) penetrating the second conductivity type layer (20) and the semiconductor layer (3), and are arranged periodically; and an insulating film (11, 16) arranged in the third trenches (21).
    [4]
    The semiconductor device with the JFET unit according to claim 3, wherein: a surface of the layer (20) of the second conductivity type in the outer resistive part (R2), and respective surfaces of the source layer (5), the channel layer (8) and the upper gate layer (9) in the cell part (R1) is in the same plane.
    [5]
    The semiconductor device with the JFET unit according to any one of the preceding claims 1 to 4, comprising: a cell part (R1) in which the JFET unit is formed; an outer peripheral breakdown proof portion (R2) enclosing the cell portion (R1); and an element separating portion (R3) arranged at a boundary position between the cell portion (R1) and the outer resistive portion (R2), wherein in the outer resistive portion (R2), the source layer (5) is removed, and removal of the source layer (5) exposes a surface of the semiconductor layer (5). 3), and a layer (20) of a second conductivity type is arranged on the exposed surface of the semiconductor layer (3), and in the element separating part (R3) an extraction electrode (32) is electrically connected to the semiconductor layer (3) via the layer (20). ) of the second type of conductivity.
    [6]
    The semiconductor device with the JFET unit according to any one of the preceding claims 1 to 4, comprising: a cell part (R1) in which the JFET unit is formed; an outer resistant part (R2) enclosing the cell part (R1); and an element separating part (R3) arranged at a boundary position between the cell part (R1) and the outer resistant part (R2), the element separating part (R3) comprising: an extraction electrode (32) electrically connected to the semiconductor layer (3). ) located in the element separating part (R3); a fourth trench (50) penetrating the source layer (5) located in the element separating part (R3), and extending into the semiconductor layer (3) located in the element separating part (R3); and a contact layer (51) embedded in the fourth trench (50), the extraction electrode (32) being electrically connected to the semiconductor layer (3) via the contact layer (51).
    [7]
    The semiconductor device with the JFET unit according to any one of the preceding claims 1 to 6, comprising: a cell part (R1) in which the JFET unit is formed; an outer resilient portion (R2) enclosing the cell portion (R1), wherein in the outer resilient portion (R2), the source layer (5) is removed, and removal of the source layer (5) exposes a surface of the semiconductor layer ( 3), and a layer (20) of the second conductivity type is arranged on the exposed surface of the semiconductor layer (3); and a Schottky diode comprising a fifth trench (60) having a frame shape surrounding the cell portion (R1), and penetrating the second conductivity type layer (20) and the semiconductor layer (3) and extending into the operating layer (2), and a Schottky electrode (61) arranged in the fifth trench (60) and electrically connected to the operating layer (2). 10 15 20 25 30 35 28
    [8]
    A manufacturing method for a semiconductor device with a JFET (junction field-effect transistor), the manufacturing method comprising: preparing a semiconductor substrate (6) comprising: a base part (1) having a main surface made of a semiconductor material, and having a first conductivity type ; an operating layer (2) formed above the base portion (1) by epitaxial growth, and having the first type of conductivity; a semiconductor layer (3) formed above the operating layer (2) and having a second conductivity type; a source layer (5) formed above the semiconductor layer (3), which has an impurity concentration greater than the drift layer (2), and has the first conductivity type; forming a first trench (7) which penetrates the source layer (5) and the semiconductor layer (3) and extends into the operating layer (2); forming a channel layer (8) having the first conductivity type on a surface of the semiconductor substrate (6), the surface comprising an inside of the first trench (7); forming a second trench (13) separate from the first trench (7), so that the second trench (13) penetrates the channel layer (8) and the source layer (5) and extends into the semiconductor layer (3) ; forming a layer (44) of the second conductivity type in the first ditch (7) and in the second ditch (13), the layer (44) of the second conductivity type being formed on a surface of the channel layer (8) in the first ditch (7). ); removing the second conductivity type layer (44) and the channel layer (8) above the source layer (5) by planarizing a surface of the semiconductor substrate (6) after forming the second conductivity type layer (44), so that an upper gate layer (9) is formed in the first ditch (7) and a contact embedded layer (14) is formed in the second ditch (13), the upper gate layer (9) being formed from the channel layer (8) and the layer (44) of second the conductivity type in the first trench (7), the contact-embedded layer (14) being formed from the layer (44) of the second conductivity type in the second trench (13); forming an intermediate insulating film (11) on a surface of the semiconductor substrate (6) and forming a plurality of contact holes (11a to 11c) for exposing the source layer (5), the upper gate layer (9) and the contact embedded, respectively. the layer (14) of the intermediate insulating film (11); forming a source electrode (15) electrically coupled to the source layer (5) through a first of the contact holes (11a to 11c), a first gate wire (12) electrically coupled to the upper gate layer (9) ) through a second of the contact holes (11a to 11c), and a second gate wire (12) electrically connected to the contact embedded layer (14) through a third of the contact holes (11a to 11c); and forming a drain electrode (18) electrically coupled to the base portion (1) on a back side of the semiconductor substrate (6).
    [9]
    The manufacturing method of the semiconductor device with the JFET unit according to claim 8, wherein: an outer peripheral breakdown proof portion (R2) is formed so as to encircle a cell portion (R1) in which the JFET the unit must be shaped; in forming the second trench (13), the source layer (5) in the outer resistant part (R2) is removed to expose a surface of the semiconductor layer (3); in forming the second conductivity type layer (44), the second conductivity type layer (44) is formed on the exposed surface, of the semiconductor layer (3), which is exposed by removing the source layer (5); and by flattening the surface of the semiconductor substrate (6), the flattening is performed on a surface of the layer (44) of the second conductivity type formed in the outer resistant part (R2).
    [10]
    The manufacturing method of the semiconductor device with the JFET unit according to claim 9, wherein: an element separating part (R3) is formed at a boundary position between the cell part (R1) and the outer resistant part (R2); in forming the second trench (13), the source layer (5) in the element separating part (R3) is removed to expose a surface of the semiconductor layer (3); in forming the second conductivity type layer (44), the second conductivity type layer (44) is formed on the exposed surface, which is exposed by removing the source layer (5), from the semiconductor layer (3); when forming the intermediate insulating film (11) and forming the plurality of contact holes (11a to 11c), an additional contact hole (11d) is formed in the intermediate insulating film (11), for exposing the layer ( 44) of the second conductivity type in the element separating part (R3); and upon forming the source electrode (15) and the second gate wire (12), an extraction electrode (32) is formed, the extraction electrode (32) being electrically connected to the second conductivity type layer (44) through the further contact hole. (11d) formed in the intermediate insulating film (11) in the element separating part (R3).
    [11]
    The manufacturing method of the semiconductor device with the JFET unit according to claim 9, wherein: an element separating part (R3) is formed at a boundary position between the cell part (R1) and the outer resistive part (R2); when forming the second trench (13), a third trench (50) is formed in the element separating part (R3) penetrates the source layer (5) and extends into the semiconductor layer (3); in forming the second conductivity type layer (44), the second conductivity type layer (44) is formed into the third trench (50) in the element separating portion (R3); in the flattening of the surface of the semiconductor substrate (6), the flattening is performed so that the layer (44) of the second conductivity type remains only in the third trench (50) and is formed into a contact layer (51); upon forming the intermediate insulating film (11) and forming the plurality of the contact holes (11a to 11c), an additional contact hole (11d) is formed in the intermediate insulating film (11), for exposing the contact layer (51) in the element separating part ( R3); and upon forming the source electrode (15) and the second gate wire (12), an extraction electrode (32) is formed, the extraction electrode (32) being electrically connected to the contact layer (51) through the further contact hole (11d) formed in the intermediate insulating film (11) in the element separating part (R3).
    类似技术:
    公开号 | 公开日 | 专利标题
    US8946726B2|2015-02-03|Grid-UMOSFET with electric field shielding of gate oxide
    US10217858B2|2019-02-26|Semiconductor device and method of manufacturing semiconductor device
    SE1150867A1|2012-03-31|Semiconductor device with JFET and manufacturing method thereof
    US9318619B2|2016-04-19|Vertical gallium nitride JFET with gate and source electrodes on regrown gate
    US9406743B2|2016-08-02|Semiconductor device with counter doped layer
    JP2013012707A|2013-01-17|Semiconductor device manufacturing method and semiconductor device
    US8921903B2|2014-12-30|Lateral junction field-effect transistor
    CN113178479A|2021-07-27|Semiconductor device with a plurality of semiconductor chips
    EP2378558A1|2011-10-19|Semiconductor device
    JP4051971B2|2008-02-27|Silicon carbide semiconductor device and manufacturing method thereof
    US20120043606A1|2012-02-23|Semiconductor device and method for manufacturing same
    TWI608617B|2017-12-11|Semiconductor device and method for manufacturing the same
    JP2017063079A|2017-03-30|Silicon carbide semiconductor device and method of manufacturing the same
    JP2011171421A|2011-09-01|Semiconductor device and method for manufacturing the same
    WO2007034547A1|2007-03-29|Trench gate power mosfet
    JP4089185B2|2008-05-28|Silicon carbide semiconductor device and manufacturing method thereof
    JP2020098836A|2020-06-25|Semiconductor device
    JP2021040042A|2021-03-11|Superjunction semiconductor device and manufacturing method thereof
    US20180114836A1|2018-04-26|Semiconductor device and method of manufacturing semiconductor device
    JP2010199424A|2010-09-09|Semiconductor device, and manufacturing method of the same
    JP6206058B2|2017-10-04|Semiconductor device
    CN111295763A|2020-06-16|Wide band gap semiconductor device
    同族专利:
    公开号 | 公开日
    US20120080728A1|2012-04-05|
    JP5310687B2|2013-10-09|
    US8519452B2|2013-08-27|
    SE535772C2|2012-12-11|
    DE102011083441A1|2012-04-05|
    JP2012079795A|2012-04-19|
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    JPS63124762A|1986-11-13|1988-05-28|Tokyo Electric Co Ltd|Stepping motor|
    JPS63124762U|1987-02-04|1988-08-15|
    JP2002270841A|2001-03-13|2002-09-20|Denso Corp|Semiconductor device and manufacturing method of the same|
    JP2004134547A|2002-10-10|2004-04-30|Hitachi Ltd|Semiconductor device|
    US6878993B2|2002-12-20|2005-04-12|Hamza Yilmaz|Self-aligned trench MOS junction field-effect transistor for high-frequency applications|
    SE527205C2|2004-04-14|2006-01-17|Denso Corp|Process for manufacturing semiconductor device with channel in silicon carbide semiconductor substrate|
    DE102005023891B4|2004-05-24|2009-08-27|DENSO CORPORATION, Kariya-shi|A method of manufacturing a silicon carbide semiconductor device and a silicon carbide semiconductor device|
    JP4696471B2|2004-05-24|2011-06-08|株式会社デンソー|Silicon carbide semiconductor device and manufacturing method thereof|
    JP4857527B2|2004-05-24|2012-01-18|株式会社デンソー|Method for manufacturing silicon carbide semiconductor device|
    US7417266B1|2004-06-10|2008-08-26|Qspeed Semiconductor Inc.|MOSFET having a JFET embedded as a body diode|
    JP4899405B2|2004-11-08|2012-03-21|株式会社デンソー|Silicon carbide semiconductor device and manufacturing method thereof|
    JP5499449B2|2008-07-29|2014-05-21|株式会社デンソー|Silicon carbide semiconductor device and manufacturing method thereof|
    JP5326405B2|2008-07-30|2013-10-30|株式会社デンソー|Wide band gap semiconductor device|
    US8373208B2|2009-11-30|2013-02-12|Alpha And Omega Semiconductor Incorporated|Lateral super junction device with high substrate-gate breakdown and built-in avalanche clamp diode|
    JP2011254387A|2010-06-03|2011-12-15|Rohm Co Ltd|Ac switch|JP5724945B2|2012-05-18|2015-05-27|株式会社デンソー|Method for manufacturing silicon carbide semiconductor device|
    WO2014087601A1|2012-12-03|2014-06-12|パナソニック株式会社|Semiconductor device and method for manufacturing same|
    TWI559534B|2014-11-03|2016-11-21|Hestia Power Inc|Silicon carbide field effect transistor|
    KR101807122B1|2015-09-02|2018-01-10|현대자동차 주식회사|Method for manufacturing semiconductor device|
    JP6696329B2|2016-07-05|2020-05-20|株式会社デンソー|Silicon carbide semiconductor device and manufacturing method thereof|
    JP2019071314A|2017-10-05|2019-05-09|国立研究開発法人産業技術総合研究所|Semiconductor device|
    JP2020119939A|2019-01-21|2020-08-06|株式会社デンソー|Semiconductor device|
    法律状态:
    2020-05-05| NUG| Patent has lapsed|
    优先权:
    申请号 | 申请日 | 专利标题
    JP2010221449A|JP5310687B2|2010-09-30|2010-09-30|Semiconductor device provided with junction field effect transistor and manufacturing method thereof|
    [返回顶部]